This invention relates generally to gate array cell architecture and, more particularly, to CMOS gate array cell architecture for double metal CMOS processing that provides for straight line cell metal interconnects or metal interconnect paths in one metal level between cells for substantially most circuit designs and without the need for separate routing channels.
The core of a M.sup.2 CMOS gate array comprises the placement of a multitude of gate array basic cells in orthogonal directions, such as, in consecutive rows and/or columns. The gate array basic cell per se is generally comprised of two or more n-channel and p-channel transistor pairs. A gate array macrocell comprises the interconnection of transistor pairs in one or more basic cells employing metal-1 or M-1 and metal-2 or M-2 interconnect layers. There is a preferred travel direction associated with each of these metal layers so that, for example, M-1 travels only in the vertical direction and M-2 travels only in the horizontal direction or vice versa.
A circuit design is fulfilled for a gate array by automatically placing the macrocells on possible basic cell sites and routing them together employing two metal interconnect layers. In conventional gate arrays, the amount of M-1 and M-2 employed in order to build macrocells generally completely covers the entire area of the basic cell thereby leaving no room for metal routing. As a result, in order to provide room for routing metals, one approach is to provide an area adjacent to the basic cells which is void of any basic cells. This void area is referred to in the art as a routing channel and a gate array constructed with such a channel is generally referred to as a channeled gate array. Another approach is to fill the entire array with basic cells, but leave alternate rows or columns of basic cells empty as they become needed for routing. Such as scheme is illustrated in U.S. Pat. No. 4,884,118. A still further approach is illustrated in U.S. Pat. No. 4,682,201 wherein a lateral shift relative to complementary transistor pairs of gate array basic cells is provided so that matched source/drain interconnects can be accomplished with straight line connections as illustrated in FIG. 5 of that patent. However, in many cases such a lateral shift in complementary transistor pairs results in a lost complement transistor pair in each basic cell. This is illustrated in the connected circuit device of FIG. 5 of U.S. Pat. No. 4,682,201 wherein the p region to the extreme right and the n region to the extreme left of connected macrocell remain unconnected and not able to be placed into use. Therefore, these areas throughout the array are wasted, particularly in the case of circuit designs utilizing complementary transistor pairs.
As a specific example of the foregoing, gate array basic cells generally comprise two or more n-channel and p-channel transistor pairs, such as, illustrated in FIG. 1. FIG. 1 depicts the physical layout of a typical four transistor gate array basic cell comprising two transistor pairs. The source/drain of p-channel transistors 10 are labelled p.sub.1, p.sub.2 and p.sub.3 and the source/drain of n-channel transistors 12 are labelled n.sub.1, n.sub.2 and n.sub.3. Polysilicon lines 14 and 16 form the gate electrode structure for the four transistors 10 and 12. When considering that formed metal tracks for the metal interconnects run in orthogonal directions vertically and horizontally, it is readily clear that there is no possibility for a straight line interconnect between cells that will cross all source and drain areas of both p and n-channel transistors 10 and 12 and their gates. As an example, in FIG. 1, in order to connect regions p.sub.1, p.sub.3 and n.sub.3 to form a circuit structure, it is not possible to employ a single straight line interconnect and, therefore two layers of metal at different levels are necessary to accomplish such a connection.
FIG. 2 illustrates a schematic diagram of a conventional transistor circuit device comprising a CMOS transmission gate pair, which is often employed in gate array macrocells. In this circuit, A and B are input signals to transmission gates 16 and 18 which are complementary pairs of CMOS transistors. The output of gates 16 and 18 are connected to output Z. CK and CK are controlled or clock inputs to drive the gates of the complementary transistor pairs comprising transmission gates 16 and 18 and are determinative of whether either input signal A or input signal B is provided at output Z.
FIG. 3 is a physical layout of the transistor circuit device of FIG. 2 based on the conventional basic cell of FIG. 1 provided with an interconnect pattern for the transistor circuit device of FIG. 2. The metal interconnects require two different levels of metal because there is a necessary change in direction of the metal interconnects to complete the circuit unless one goes outside the basic cell which is not a viable solution because of possible interference with circuitry in an adjacent basic cell. Thus, FIG. 3 illustrates the complexity of interconnections for forming this circuit device in conventional gate arrays. In this example, the direction of the first metal layer, M1, is horizontal and the direction of the second metal layer, M2 is vertical. As can be seen from FIG. 3, the result is that the entire area of the basic cell of FIG. 1 is substantially taken up by the necessary placement of the cell metal interconnects.
It is an object of this invention to provide a new basic cell layout that substantially simplifies the metal interconnects employed in connection with gate array basic cells.
It is another object of this invention to provide for substantially all interconnects to be adapted to run or be placed in a single metal interconnect travel direction.
It is another object of this invention to minimize the amount of metal interconnects necessary to create gate array macrocells.
It is another object of this invention to maximize the porosity of gate array macrocells for routing.
It is a still further object of this invention to eliminate the need for separate routing channels adjacent to macrocell areas employed in conventional gate cell array architecture.
It is a further object of this invention to provide for higher utilization rates over conventional basic cell architectures.